1. Field of the Invention
This invention relates to the fabrication of wirebonds to electrical devices (including optoelectronic devices), and, more particularly to the fabrication of wirebonds to integrated circuits (ICs).
2. Discussion of the Related Art
The fabrication of electrical semiconductor devices or chips typically begins with front-end processing, which may include one or more of the following steps: epitaxial growth of semiconductor layers on a wafer or substrate, photolithographically patterning the layers and/or the substrate, doping the layers and/or the substrate to form various device regions, depositing and shaping dielectric layers, depositing and shaping electrical conductors and/or bond pads, and dicing the wafer into individual devices or chips. Subsequently, the devices undergo back-end processing, which may include forming wirebonds to the bond pads, encapsulating the wirebonds and devices in an electrically insulating material, and packaging the devices in suitable ceramic, plastic or metal containers.
In the IC industry, a multiplicity of side-by-side wirebonds is often formed along the edges of each IC chip by means of a wire-bonding machine (e.g., a ball-bonding or wedge-bonding machine). The number of wirebonds is related to the number of input/output (I/O) signals that a particular IC is required to accommodate. As the number of I/Os increases for a particular chip size (i.e., as the lead count increases), the diameter of each wirebond must decrease (e.g., from 1 mil to 0.5 mil) in order to maintain sufficient spacing between them. But finer (i.e., thinner) wirebonds are physically less stable, especially during the encapsulation process when the injected encapsulant may displace one or more of them (known as wire sweep) sufficiently to cause adjacent wirebonds to contact one another and thereby form an undesirable short circuit.
One solution to this problem might be to change the encapsulant to a material that causes less wire sweep during the encapsulating (i.e., molding) process of finer wirebonds. Unfortunately, changing the encapsulant implies increasing cost, which is undesirable in the cost-sensitive, highly competitive IC industry.
Another solution, is to coat the wires with insulative material before encapsulation, as described by P. M. Weiler et al., in U.S. Pat. No. 5,527,742 issued on Jun. 18, 1996, but this approach suffers from cross-talk problems because the way that insulated wires cross one another differs from one chip to another. This patent is incorporated herein by reference.
Thus, a need remains in the art for a process that enables high-density, small-diameter wirebonds to be formed with less wire sweep and without having to utilize expensive encapsulants or having to insulate the wires first.